1. Field of the Invention
The present invention relates to a method of fabricating a microelectronic device, and more particularly, to a method of fabricating a microelectronic device using super critical fluid.
2. Discussion of the Related Art
A microelectronic device such as a highly-integrated semiconductor device is structured such that elements in its upper and lower portions are connected to each other via a multilayer structure of metal interconnections. Since a metal layer is relatively difficult to etch in comparison with an insulating layer, a dual damascene process is used to pattern the metal layer. U.S. Pat. No. 6,057,239, by Fei Wang, et. al. which is incorporated herein by reference, discloses a dual damascene process using sacrificial spin-on material.
Hereinafter, a method of forming a dual damascene interconnection according to a prior art technique will be explained in reference to FIGS. 1A to 1G.
Referring to FIG. 1A, a semiconductor substrate 10 is prepared with lower metal interconnections 11 thereon, which are insulated by an insulating layer 12. Then, an etch stop layer 13, an interlayer insulating layer 14, and a capping layer 15 are sequentially formed on the lower metal interconnections 11 and the insulating layer 12.
Referring to FIG. 1B, a first photoresist pattern PR1 for defining a via is formed on the capping layer 15 of FIG. 1A. Then, the capping layer 15 and the interlayer insulating layer 14 are etched using the photoresist pattern PR1 as an etch mask. Thus, one or a plurality of openings V are formed inside the etched interlayer insulating layer 14a and the etched capping layer 15a. Each opening V comprises a via portion V1 and a preliminary trench portion V2 extending upward from the via V1.
Referring to FIG. 1C, the photoresist pattern PR1 of FIG. 1B is removed, and a sacrificial layer 16 is formed on the exposed surfaces of the semiconductor device so as to fill the openings V. Then, a second photoresist pattern PR2 is formed on the sacrificial layer 16 for defining a trench. The sacrificial layer 16 is formed to prevent the lower metal interconnection 11 from being exposed too early because the etch stop layer 13, which has a lower etch selectivity relative to the interlayer insulating layer 14a, is removed during the etching process of etching the interlayer insulating layer 14a in forming the trench.
Referring to FIG. 1D, the sacrificial layer 16, the capping layer 15a, and the interlayer insulating layer 14a as seen in FIG. 1C are etched using the photoresist pattern PR2 as an etch mask. Thus, a trench T, generally in the same region of the device as the preliminary trench V2, is formed inside the capping layer 15a and the interlayer insulating layer 14a. Following this etching step, the sacrificial layer portions 16a and 16b remain respectively inside the via V1 and on the capping layer 15a. 
Referring to FIG. 1E, the photoresist pattern PR2 of FIG. 1D is removed.
Referring to FIG. 1F, the sacrificial layer portions 16a and 16b, which remained inside the via V1 and over the interlayer insulating layer 14a in FIG. 1E, are now removed. The sacrificial layers 16a and 16b are typically removed by a wet etching process. For example, if the interlayer insulating layer 14 is composed of SiOC:H, and the sacrificial layer 16 is composed of hydrogen silsesquioxane (HSQ), the sacrificial layers 16a, 16b are removed by a wet etching process using diluted hydrofluoric acid. During the initial part of the process wherein the sacrificial layers 16a, 16b are removed by the wet etching process, while the etch stop layer 13 is still covered by the sacrificial layer 16a, the capping layer 15a having exposed sidewalls is typically damaged by wet etchant such that its width is reduced. That is, if a width of the capping layer 15a before the wet etching process is performed is ‘W1’, a width of the capping layer 15a after the wet etching process is performed is reduced to a smaller width ‘W2’. Further, an upper surface of the interlayer insulating layer 14a is also typically damaged by the wet etchant, which penetrates through into the interface between the interlayer insulating layer 14a and the capping layer 15a, thereby generating an undercut U. Due to the undercut U, a lifting of the capping layer 15a from contact with layer 14a may occur.
Further, the interlayer insulating layer 14a is ordinarily formed of a low-k dielectric layer in order to reduce a parasitic capacitance between the interconnections. The low-k dielectric layer typically has porous and high moisture absorbance properties. As described above, while the sacrificial layers 16a, 16b are being removed by the wet etching process, moisture commonly penetrates through into the interlayer insulating layer 14a, thereby generating silanol groups (Si—OH bonds). Formation of such silanol groups increases a dielectric constant of the interlayer insulating layer 14a. Therefore, it is usually necessary to perform an additional annealing process at a temperature higher than 400° C. in order to remove the silanol groups.
Referring to FIG. 1G, the etch stop layer 13 under the via V1 of FIG. 1F is now selectively removed. Thus, the lower metal interconnections 11 are exposed along the etched portions of etch stop layer 13a. Then, the trench T and the via V1 are filled with a conductive layer, thereby forming an upper interconnection 17. The upper interconnection 17 is formed by sequentially depositing a seed layer, a diffusion barrier layer, and a metal layer, and then performing deposition and polishing processes.
The conventional formation method of a dual damascene interconnection described as above has a number of problems and limitations, including the facts that a leakage current is normally increased, and the seed layer and the diffusion barrier layer are usually poorly deposited, thereby causing discontinuity of layers, due to the effects of the wet etching process for removing the sacrificial layers 16a, 16b, during which the capping layer 15a may be reduced in width and/or lifted.
With increasingly high integration of modern microelectronic devices, it is desirable to reduce the distance between metal interconnections. However, if the distance between metal interconnections becomes too narrow, a cross talk may occur between the metal interconnections, and a parasitic capacitance between the metal interconnections having the insulating layer formed therebetween is thereby increased. As a result, electric signals through the metal interconnections are poorly transmitted, or a transmission speed of such signals is reduced. In the formation method of a dual damascene interconnection, a parasitic capacitance can be reduced when the interlayer insulating layer 14 is composed of a low-k dielectric material. Such formation method has a problem, however, in that silanol groups are formed inside the low-k dielectric interlayer insulating layer 14a of porous property during the wet etching process of removing the sacrificial layers 16a, 16b, thereby increasing a dielectric constant. The silanol groups inside the interlayer insulating layer 14a can be removed through heating the partially formed microelectronic device at a temperature above 400° C., but some portions of other elements are then attacked and damaged due to the heating. Therefore, it is desired in this art to find a method of removing a sacrificial layer without damaging the capping layer on the interlayer insulating layer and without increasing the dielectric constant of the interlayer insulating layer.
These and other problems with and limitations of the prior art processes in this field are addressed in whole, or at least in part, by the methods and techniques of this invention.